Modern high-density integrated circuits are known to be vulnerable to damage from the ESD from a charged body (human or otherwise) as the charged body physically contacts an integrated circuit (IC). ESD damage occurs when the amount of charge exceeds the capability of the conduction path through the IC. The typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate-junction shorting (e.g., in the metal-oxide-semiconductor (MOS) context).
It is often difficult to analyze the ESD vulnerability of a given IC, because the charge versus time characteristics of ESD events vary quite widely among the various sources of ESD. The ESD protection of modern ICs is characterized according to multiple models, each of which are intended to model a particular type of ESD event. The Human Body Model (HBM) models discharge of a charged human contacting an IC, and is realized by a 150 pF capacitance discharging into the IC within about 100 nsec. The Machine Model (MM) models discharge from metal objects such as IC test and manufacturing equipment, and generally uses a higher capacitance with lower internal resistance than the HBM, resulting in even faster discharge times. The Charged Device Model (CDM) models a discharge from a charged IC to ground, rather than a discharge to the IC. These differences in discharge characteristics and polarity manifest themselves in different failure manifestations within the IC; indeed the conduction may follow different paths within the device.
ESD protection devices generally operate by providing a high capacity current conduction path, so that the brief but massive ESD charge may be safely conducted away from structures that are not capable of handling the ESD event. In some cases, ESD protection is inherent to the particular terminal, as in the case of a power supply terminal which may provide an extremely large area p-n junction capable of conducting the ESD charge. Input and output (functional) terminals, on the other hand, typically have a separate ESD protection device added in parallel to the functional terminal. The ideal ESD protection device turns on quickly in response to an ESD event, with large current conduction capability, but remains off and presents essentially no load or leakage during normal IC operation.
SCR-based ESD protection devices are known. For bidirectional protection, two SCRs are provided in parallel. However, for an SCR, it can be difficult to isolate the current flow paths, particularly during an international electrotechnical commission (IEC) strike. For example, during a negative strike, it can be difficult to prevent current from flowing into the substrate, which can cause current to reach and thus damage nearby devices on the IC.
Moreover, high voltage system-level (IEC) ESD protection requirements place stringent constraints on ESD protection device design. In particular, a suitably high breakdown voltage must be maintained while enabling high current to flow during the strike. Some high voltage MOS devices are particularly ESD sensitive. For example, it has been observed that remote drain MOS devices such as drain extended MOS (DEMOS) devices provide very poor inherent ESD protection.
Remote drain MOS devices include DEMOS devices, and Double-Diffused MOS (DMOS) devices including Lateral Double-Diffused MOS (LDMOS) devices. Such remote drain MOS devices can include a p-type buried layer (PBL) underneath the drain regions to provide higher source-to-drain breakdown voltages while allowing power efficient switch operation due to the known reduced surface field (“resurf”) principle.